Espressif Systems /ESP32-S3 /SENSITIVE /CORE_1_PIF_PMS_CONSTRAIN_2

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Interpret as CORE_1_PIF_PMS_CONSTRAIN_2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER

Description

Core1 access peripherals permission configuration register 2.

Fields

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT

Core1 access bt permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0

Core1 access i2c_ext0 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0

Core1 access uhci0 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST

Core1 access slchost permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT

Core1 access rmt permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT

Core1 access pcnt permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC

Core1 access slc permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC

Core1 access ledc permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP

Core1 access backup permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB

Core1 access bb permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0

Core1 access pwm0 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP

Core1 access timergroup permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1

Core1 access timergroup1 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER

Core1 access systimer permission in world0.

Links

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